The invention relates generally to a method for multi-layer integrated circuit design layout, and more specifically, to a method in a data processing system for timing based net constraints tagging within a multi-layer integrated circuit design layout. The invention relates further to a system for timing based net constraints tagging within a multi-layer integrated circuit design layout, and a computer program product.
Today's electronic components are in many cases integrated circuits of semiconductor devices. Hundreds, or millions, of such semiconductor devices may be integrated in one single chip. In order to design the circuits and the layout of individual functional components or sub-groups, designers use a variety of software based tools. The tools may be designed to use the electronic components or groups of components as functional blocks with input pins and output pins and help the designers to place the components or groups of components on, respectively, the chip surface. The functional blocks with all its characteristics—e.g., individual delays—are typically provided by related libraries. The individual functional blocks may be interconnected with wires. Such a mash of functional blocks and their wiring may be called a net. Due to the length of the wires, the travel time of signals, expected heat dissipation, and circuit delay times, a highly sophisticated layout process has to be applied in order to make a chip finally work as a whole including all functional blocks and sub-blocks.
Due to the high number of functional blocks and the nearly limitless options to place the functional blocks on, respectively, the chip, wiring becomes a critical constraint. The wiring itself allows for multiple design choices such as the kind of metal chosen or width or height of the wire. It may also be noted that different wiring layers (isolated from each other) may be present in real chips. Additionally, the minimum and maximum width and height may be layer-dependent.
Thus, a large number of dependencies have to be reflected in the design of more and more complex chips. Detecting physical limitations not as early as possible in a design process may be time consuming and not cost effective.